I’m definitely getting behind on the proper tests. I already have another milestone.
Run at 2017-05-30 15:32:35 +0000 Z80all instruction exerciser hl,.... OK add hl,.......... OK add ix,.......... OK add iy,.......... OK aluop a,nn.................... OK aluop a,<b>.. OK aluop a,..... OK aluop a,(+1)........... OK bit n,(+1)............. OK bit n,<b>.... OK cpd........................ OK cpi........................ OK ............. OK a................... OK b................... OK bc.................. OK c................... OK d................... OK de.................. OK e................... OK h................... OK hl.................. OK ix.................. OK iy.................. OK l................... OK (hl)................ OK sp.................. OK (+1)......... OK ixh................. OK ixl................. OK iyh................. OK iyl................. OK ld ,(nnnn)............. OK ld hl,(nnnn).................. OK ld sp,(nnnn).................. OK ld ,(nnnn)............. OK ld (nnnn),............. OK ld (nnnn),hl.................. OK ld (nnnn),sp.................. OK ld (nnnn),............. OK ld ,nnnn......... OK ld ,nnnn............... OK ld a,.............. OK ld <b>,nn.... OK ld (+1),nn............. OK ld <b>,(+1)...... OK ld ,(+1).......... OK ld a,(+1).............. OK ld ,nn....... OK ld ,........ OK ld ,........ OK ld a,(nnnn) / ld (nnnn),a..... OK ldd (1).................... OK ldd (2).................... OK ldi (1).................... OK ldi (2).................... OK neg........................... OK ..................... OK ........... OK shf/rot (+1)........... OK shf/rot <b>.. OK n,..... OK n,(+1)....... OK ld (+1),<b>...... OK ld (+1),.......... OK ld (+1),a.............. OK ld (),a................ OK Tests complete 47394502273 t-states in 217.548205865 secs for 217.857472483183 MHz
The zexall test now works. I had some tricky issues surrounding an undocumented register – the wz register and the X and Y flags, but it’s all good. I still have a lot of instructions to implement, especially with respect to relative jumps and interrupts, all the IO instructions. IO instructions are a new thing for me, the 6502 doesn’t have them.
The speed has dropped a bit. I think this is largely due to some new operators I introduced to make the code more succinct. For example, all the memory reads for instructions went along the lines of:
readData(address: pc) pc = pc &+ 1
Now look more like
readData(address: pc&++)
The &++ operator is probably not being inlined.
